Komuravelli and Sinclair Win Qualcomm Innovation Fellowship
Computer science Ph.D. students Rakesh Komuravelli and Matthew Sinclair have recently received one of only eight $100,000 Qualcomm Innovation Fellowships for 2012. The funding will support their work to address various hardware challenges in heterogeneous architectures. Qualcomm Innovation Fellowships help students pursue futuristic innovative ideas, while promoting Qualcomm Incorporated’s core values of innovation, execution, and teamwork.
Power issues in hardware architectures have become a major impediment to chip manufacturers’ ability to increase performance in new generations of processors. While multicore architectures offer one model towards addressing the rising power consumption problem, such architectures are still unable to utilize the entire chip area within a reasonable power budget.
In contrast, heterogeneous systems, where components are specialized for various problem domains, offer a more power-efficient solution. Because the individual components are optimized for performing their domain-specific computations, they offer the promise to alleviate today’s power dissipation problems. These systems also offer the ability to run different parts of an application on different optimized parts of the architecture, resulting in faster performance.
Komuravelli and Sinclair view heterogeneous environments as critical to moving forward the state-of-the-art, especially for applications in areas like voice and image recognition, vision, image processing, and machine learning, among others.
On the downside, heterogeneous systems can be a challenge to program, due to the many differences in instruction sets, memory models, and functionality, among others, requiring complex programming models and scheduling algorithms.
In their work, Komuravelli and Sinclair are targeting memory hierarchies in heterogeneous systems, aiming to improve data transfer, data organization, coherence, and reconfigurability of the memory hierarchy.
“The memory hierarchy of today’s heterogeneous systems is usually loosely coupled, resulting in unnecessary data transfer between components,” explains Komuravelli.
“Those types of designs are also impractical for offloading small workloads to the accelerators,” continues Sinclair. “Therefore, if we want to see more power efficiency, and greater applicability, we need to make these kinds of systems more tightly coupled.”
Their work on the project builds on prior work on the DeNovo memory model, which used program-level annotations to allow flexible data movement that resulted in better power and performance. The team hopes to apply similar software-aware techniques through abstractions for heterogeneous architectures.
Initially, Komuravelli and Sinclair will be integrating CPUs, GPUs, and DSPs into a tightly coupled architecture, though they hope to extend their architecture to include FPGAs and more domain-specific accelerators in the future.
“Heterogeneity and specialization will be key enablers for future performance increases,” says Sarita Adve, a professor of computer science at Illinois and co-mentor for this project. “Most past research in this area, however, has focused on computation. In the next generation of machines, the action is going to be in data and communication, be it for raw performance or energy efficiency. Matt and Rakesh are exploring some very novel ideas on how to unify the memory system of a heterogeneous set of compute cores and accelerators so that we can get the efficiency of specialization with the programmability of more general-purpose data organizations.”
“This work is part of a broader project that aims to address the programmability and software portability problems for heterogeneous computing,” says Illinois computer science professor and project co-mentor Vikram Adve. “By examining memory system design choices hand-in-hand with redesigning the programming interfaces and compiler optimization techniques, energy efficiency and performance can both be maximized.”
Komuravelli, an expert in hardware-software co-design and cache coherence protocols, and Sinclair, an expert in GPUs and memory systems, will collaborate on the project with their advisors Sarita Adve and Vikram Adve, and alumnus Pablo Montesinos (Ph.D. 2009), their Qualcomm mentor.