An Illinois-Intel Partnership Leads to Prototype for Debugging Innovations
7/16/2013 10:37:00 AM
In a major collaboration, CS Professors Josep Torrellas and Sam King, together with Intel researchers will unveil a hardware prototype for recording and deterministically replaying parallel programs at the International Symposium on Computer Architecture (ISCA) in June 2013. This system enables the ability to re-execute a program exactly in the same way, and identify where a bug occurred or a security intrusion started. This prototype is called QuickRec, and is composed of an FPGA implementation of an Intel multicore with full support from the Linux operating system.
A common problem with parallel computer software has been the presence of software bugs. Programmers introduce them accidentally as they write parallel programs, and they are often very hard to root out.
Other program malfunctions are not so innocently introduced. They are the result of malicious intrusions into the software system to disrupt the correct execution of the program. They are also often hard to identify and eliminate.
Researchers and industry have long been interested in new, innovative ways to help combat these accidental bugs and these malicious intrusions into the software. QuickRec is an innovative design that promises to change we way we solve these problems.
CS Professor Josep Torrellas said, “As you are running your program, when you detect a bug, you can use QuickRec to go back and trace the bug—how it came in. If you see a security intrusion, you also go back and see how it arose. QuickRec allows you to go back and see exactly how it got there.”
QuickRec could point toward the next level of innovation in performance monitoring and debugging support for processors. A key element of QuickRec is that it does not adversely impact processing speed. “It is just a hardware device that you install to monitor the machine,” said Professor King. “It doesn’t slow the machine down.”
Torrellas will also present a second paper at ISCA on a low overhead hardware approach to synchronize processors in a multicore. The scheme, called WeeFence eliminates practically all of the stall that processors suffer as they use fences for synchronization.
The QuickRec and WeeFence projects are sponsored by the Illinois-Intel Parallelism Center (I2PC), a university-industry partnership that works to advance the state of the art in parallel architectures, software, and applications.