CS 231
CS 231 - Computer Architecture I
Fall 2012
| Title | Rubric | Section | CRN | Type | Hours | Times | Days | Location | Instructor |
|---|---|---|---|---|---|---|---|---|---|
| Computer Architecture I | CS231 | X | 30105 | LEC | 3 | - |
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Official Description
Fundamentals of computer architecture, working up from the logic gate level: combinational and sequential networks; computer arithmetic; arithmetic-logic units; memory organization; control unit design. Course Information: Credit is not given for both CS 231 and ECE 290. Prerequisite: CS 125.
Subject Area
- Architecture / Hardware / Embedded Systems
Course Director
Learning Goals
Convert between decimal, binary, octal, and hexadecimal representations of integers (a)
Understand two's complement representation of integers and determine whether overflow occurs in arithmetic operations (a)
Understand the operation of discrete logic gates (a)
Analyze a combinational network using Boolean expressions (a)
Convert a verbal specification into a Boolean expression (c, e)
Understand basic properties of Boolean algebra: duality, complements, standard forms (n)
Apply Boolean algebra to prove identities and simplify expressions (a, e)
Use Karnaugh maps to find minimal sum-of-products and products-of-sums expressions (e)
Design combinational networks that use NAND, NOR, and XOR gates (c, e)
Design with MSI components such as encoders, decoders, multiplexers, adders, arithmetic-logic units, ROMs, and programmable logic arrays (c, e)
Understand the operation of latches; clocked, master-slave, and edge-triggered flip-flops; shift registers; and counters (a)
Plot and interpret timing diagrams (a, b)
Determine the functionality of sequential circuits from state diagrams and timing diagrams (a, b)
Translate sequential circuit specifications into state diagrams (c, e)
Design sequential circuit components (latches, flip-flops, registers, synchronous counters) using logic gates (c, e)
Synthesize general sequential circuits (c, e)
Understand tradeoffs in register and counter design (c)
Understand the operation of random access memories (a)
Synthesize a large memory from smaller memories and decoders (c, e)
Design datapath components, including register files, buses, and functional units (c, e)
Design a hardwired control unit to implement an instruction set (c, e)
Design a microprogrammed control unit to implement an instruction set (c, e)
Understand tradeoffs between hardwired and microprogrammed control (c)
Understand instruction formats and addressing modes (a)
Understand the operation of stack instructions, control flow, and interrupts (a)
Specify new instructions and addressing modes in register transfer language (c, e)
Translate register transfer language statements into microcode (e)
Analyze the effects of individual instructions and machine-level programs (a)
Write short machine-level programs (c, e)
Topic List
Representation of information, two's complement arithmetic.
Combinational logic: switching algebra, canonical forms, Karnaugh maps, combinational network analysis and design, MSI modules.
Sequential logic: latch, flip-flop, state diagram, sequential network analysis and synthesis, register, counter, memory organization.
Computer organization: register-transfer language, arithmetic-logic unit, fetch-execute microsequences, loop, subroutine, interrupt, microprogrammed control unit.
Required, Elective, or Selected Elective
Required
Last updated
5/23/2013