Torrellas co-leads workshop on Popular Parallel Programming

3/3/2010 Cheri Helregel, Universal Parallel Computing Research Center

Torrellas leads workshop to address building parallel architectures that can enable ubiquitous parallel software systems.

Written by Cheri Helregel, Universal Parallel Computing Research Center

How can research on parallel computer architecture help enable ubiquitous parallel software systems? That’s what the Advancing Computer Architecture Research (ACAR) group explored at the first of two CRA-sponsored workshops planned for this year (http://www.cra.org/ccc/acar.php).

“Failure is not an Option: Popular Parallel Programming” was the theme for the first workshop held this past February in San Diego, CA. University of Illinois computer science professor Josep Torrellas joined Mark Oskin of the University of Washington to organize and lead this workshop.

Josep Torrellas
Josep Torrellas
Illinois computer science professor Josep Torrellas

The workshop focused on identifying and exploring key computer architecture (CA) challenges that need to be solved by 2020-25. Two industry researchers provided keynote presentations. George Almasi of IBM Research discussed a system programmer’s approach to bridging the gap between software and hardware in his presentation, “What were they thinking?” Jim Larus of Microsoft Research addressed the challenge of taming concurrency in “Should We Fear Concurrency?” Participants also addressed the roles CA academics serve in facilitating ubiquitous parallel software systems.

The second ACAR workshop will focus on Extending the Current Programming Model. More information about ACAR workshops is available on the CRA website at: http://www.cra.org/ccc/acar.php.

Josep Torrellas is an expert on multiprocessor computer architecture, parallel computing, speculative multithreading, and software and machine reliability. He has been involved in the Stanford DASH and the Illinois Cedar multiprocessor projects, led the Illinois Aggressive COMA multiprocessor, and currently leads the Bulk Multicore architecture design. The Bulk Multicore is a revolutionary multiprocessor architecture designed for programmability (http://iacoma.cs.uiuc.edu).
 


Share this story

This story was published March 3, 2010.