Illinois CS Researchers Among Teams Selected by DARPA to Unleash Power of Specialized and Reconfigurable Hardware

7/28/2018 Defense Advanced Research Projects Agency

Researchers will explore the development of flexible architectures capable of using specialized hardware to solve specific computing problems more quickly and efficiently.

Written by Defense Advanced Research Projects Agency

The general-purpose computer has remained the dominant computing architecture for the last 50 years, driven largely by the relentless pace of Moore’s Law – the transistor-scaling that has allowed for a half-century of rapid progress in electronics. As this trajectory slows, however, it has become increasingly more challenging to achieve performance gains from generalized hardware, setting the stage for a resurgence in specialized architectures.

Sarita Adve
Sarita Adve

The program managers behind DARPA’s Electronics Resurgence Initiative (ERI) have selected research teams from academia – including the University of Illinois Department of Computer Science – and industry to explore the development of flexible architectures capable of using specialized hardware to solve specific computing problems more quickly and efficiently. ERI is a five-year, upwards of $1.5 billion investment to jumpstart innovation in the electronics industry.

As a part of the ERI Architectures research thrust area, Illinois Computer Science Professor Sarita Adve, Professor and Interim Head of Department Vikram Adve, and Assistant Professor Sasa Misailovic are part of the research teams selected for the Domain-specific System on Chip (DSSoC) program, along with research teams from IBM, Oak Ridge National Labs, Arizona State University, and Stanford University.

Vikram Adve
Vikram Adve

Assistant Professor Christopher Fletcher is part of the teams chosen for the Software Defined Hardware (SDH) program, which also includes Intel, NVIDIA, Qualcomm, and STR, as well as Georgia Tech University, Stanford University, the University of Michigan, University of Washington, and Princeton University.

The SDH and DSSoC programs will explore new ways to co-optimize software and hardware without requiring more complex programming. Both programs seek to prove that there need not be a continued tradeoff between efficiency and flexibility, the hallmark of general-purpose processors.

Assistant Professor Christopher Fletcher
Assistant Professor Christopher Fletcher

Illinois researchers involved in the DSSoC group say they will be working to design cognitive heterogeneous systems that will underlie products such as smart connected vehicles.

“The Illinois team is an ideal reflection of the goals of the project -- develop systems that combine the programmability of general-purpose computers with the hardware efficiency of specialized systems,” Sarita Adve, Vikram Adve, and Sasa Misailovic said in a statement. “Our team's expertise spans hardware and software, with past contributions that include the LLVM compiler, the Java and C++ memory models, and seminal work on approximate computing.

“For the DSSOC project, we will lead the design of the software compilation stack and the memory system architecture,” they added. “As Moore's Law ends, this is a once-in-a-lifetime opportunity to influence an entire industry that is looking for novel ways to sustain the computing performance improvements we have come to expect.”

Sasa Misailovic
Sasa Misailovic

The first domain that DSSoC researchers will explore is software-defined radio, a technology with roles in mobile and satellite communications, personal area networks, radar, and electronic warfare.

“It is critical for the DoD to have flexible, adaptable radio systems that are capable of managing and combating a complex signal environment,” said Tom Rondeau, the Microsystems Technology Office program manager leading DSSoC. “These devices must be programmable like general purpose processors, but also capable of crunching a lot of math with low power. The concept of mixing processor cores to achieve a needed level of specialization is an exciting prospect, but without the ability to enable the developer to program for these devices, their utility is limited. DSSoC is looking to address the right levels of heterogeneous processing, while simultaneously focusing on the software tools and supporting the developer ecosystem surrounding software-defined radio initially and expanding beyond that throughout the program.”

The SDH program, which Fletcher is part of, aims to develop hardware and software that can be reconfigured in real time based on the data being processed, adapting the computing architecture for the workload and data at hand.

To achieve this goal, researchers will explore reconfigurable computing architectures and software environments that can deliver specialized, data-intensive application performance without sacrificing versatility or programmability, and without the need to develop specialized circuits for each application. If successful, SDH could open a pathway to data-intensive algorithms that can run at very low cost.

“The ability to understand data and predict the world around us delivers a fundamental advantage for human nature and can lead to an asymmetric advantage for the DoD,” said Wade Shen, the program manager leading SDH who bridges the gap between hardware and software by working across DARPA’s Microsystems Technology Office and Information Innovation Office. “For problems that cannot afford the large investment required for fully custom solutions, we currently sacrifice compute efficiency by implementing solutions in the form of software on general-purpose processors or field-programmable gate arrays (FPGAs). Often, this results in application implementations that are thousands of times worse than optimal. SDH will develop runtime-reconfigurable hardware and software that enables near full-custom performance without sacrificing programmability for data-intensive algorithms.” 

SDH and DSSoC are two of six ERI “Page 3” programs – so named for their relevance to the guidance shared by Gordon Moore on the third page of his seminal 1965 research paper that articulated what became known as Moore’s Law. Designed to fulfill the post-scaling predictions made by Moore, the ERI “Page 3” Architectures programs seek to determine whether we can enjoy the benefits of specialized and application-reconfigurable circuitry while still relying on general programming constructs through integrated software-hardware co-design.

Other University of Illinois researchers are also part of the DARPA ERI awards announced July 23 during the first DARPA ERI Summit in San Francisco. They include a grant to develop foundational computing technology for next-generation autonomous defense systems being led by Professor Naresh Shanbhag of Electrical and Computer Engineering at Illinois and a researcher in the Coordinated Science Lab.

The three-day DARPA conference brought together hundreds of members of the electronics community to explore the future of the industry and its impact on national defense.

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This story was published July 28, 2018.