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CS 233 - Computer Architecture

Fall 2020

TitleRubricSectionCRNTypeHoursTimesDaysLocationInstructor
Computer ArchitectureCS233AL163733OLC40900 - 0950 M W F    Geoffrey Lindsay Herman
Computer ArchitectureCS233AL264513OLC41000 - 1050 M W F    Geoffrey Lindsay Herman
Computer ArchitectureCS233ALP72275OLC40900 - 0950 M W F    Geoffrey Lindsay Herman
Computer ArchitectureCS233ALR72276OLC41000 - 1050 M W F    Geoffrey Lindsay Herman
Computer ArchitectureCS233AYA63734OLB01200 - 1250 M    
Computer ArchitectureCS233AYA63734OD01100 - 1150 M    
Computer ArchitectureCS233AYB63735OD01200 - 1250 M    
Computer ArchitectureCS233AYB63735OLB01300 - 1350 M    
Computer ArchitectureCS233AYC63736OLB01400 - 1450 M    
Computer ArchitectureCS233AYC63736OD01300 - 1350 M    
Computer ArchitectureCS233AYD63737OLB01500 - 1550 M    
Computer ArchitectureCS233AYD63737OD01400 - 1450 M    
Computer ArchitectureCS233AYE63738OD01500 - 1550 M    
Computer ArchitectureCS233AYE63738OLB01600 - 1650 M    
Computer ArchitectureCS233AYF63739OD01600 - 1650 M    
Computer ArchitectureCS233AYF63739OLB01700 - 1750 M    
Computer ArchitectureCS233AYG63740OLB01800 - 1850 M    
Computer ArchitectureCS233AYG63740OD01700 - 1750 M    
Computer ArchitectureCS233AYH64544OD00900 - 0950 T    
Computer ArchitectureCS233AYH64544OLB01000 - 1050 T    
Computer ArchitectureCS233AYI64545OD01000 - 1050 T    
Computer ArchitectureCS233AYI64545OLB01100 - 1150 T    
Computer ArchitectureCS233AYJ64546OD01100 - 1150 T    
Computer ArchitectureCS233AYJ64546OLB01200 - 1250 T    
Computer ArchitectureCS233AYK64547OD01200 - 1250 T    
Computer ArchitectureCS233AYK64547OLB01300 - 1350 T    
Computer ArchitectureCS233AYL64548OD01300 - 1350 T    
Computer ArchitectureCS233AYL64548OLB01400 - 1450 T    

Official Description

Fundamentals of computer architecture: digital logic design, working up from the logic gate level to understand the function of a simple computer; machine-level programming to understand implementation of high-level languages; performance models of modern computer architectures to enable performance optimization of software; hardware primitives for parallelism and security. Course Information: Prerequisite: CS 125 and CS 173; credit or concurrent enrollment in CS 225.

Text(s)

Logic and Computer Design Fundamentals,
by M. Morris Mano and Charles R. Kime. (Published by Prentice-Hall), 2008.
Fourth Edition 2008 ISBN: 0-13-198926-X

Computer Organization & Design: The Hardware/Software Interface,
by David A. Patterson and John L. Hennessy. (Published by Morgan Kaufmann)
Second Edition: 1998 ISBN: 1-55860-428-6
Third Edition: 2004 ISBN: 1-55860-604-1
Fourth Edition 2008 ISBN-13: 978-0123744937

Verilog HDL: A Guide to Digital Design and Synthesis,
by Samir Palnitkar. (Published by Prentice Hall).
Second Edition:2003 ISBN: 0-13-044911-3

Learning Goals

Learning Goal 1: be able to design modest combinational circuits (20 - 30 gates) from an natural language (e.g., English) specification (2,6)
Learning Goal 2: be able to secure data through encryption using bitwise operations (2,6)
Learning Goal 3: be able to design finite state machines of moderate complexity (~10+ states) from a natural language specification. Furthermore, they should be able to implement these FSMs using a collection of gates and flip-flops. (2,6)
Learning Goal 4. be able to analyze the design of a simple processor, specify the control signals for supported instructions, and modify it to implement new instructions. (1, 6)
Learning Goal 5: be able to translate small (20 line) C programs that include recursion and pointers into MIPS assembly, observing calling conventions and stack management. (1, 2, 6)
Learning Goal 6: be able to write code that uses memory-mapped I/O and interrupts given interface documentation. (2, 6)
Learning Goal 7: be able to demonstrate an understanding of the performance pitfalls of pipelined processors with cache memory systems by predicting the performance of code fragments on simple pipelines and cache memory systems. (1, 2, 6)
Learning Goal 8: be able to optimize the cache performance of a simple loop nest through cache-aware programming techniques (2, 6)
Learning Goal 9: be able to describe how virtual memory abstracts the memory system and provides security (2, 6)
Learning Goal 10: be able to recognize synchronization, coherence, and consistency pitfalls that could impact the execution's result or performance of simple programs executing on a shared memory parallel processor. (1, 6)
Learning Goal 11: be able to work in small groups on open ended problems (2, 5, 6)

Topic List

  1. Representation of information with binary bits (e.g., Unsigned binary, 2's complement)
  2. Combinational design (e.g., truth tables, logic gates, modular design, hierarchical design)
  3. Sequential logic design (e.g., flip-flops, finite state machines)
  4. Computer organization (e.g., register files, ALUs)
  5. Assembly language programming
  6. Input/output strategies for computer architectures
  7. Pipelining (e.g., pipeline stages plus resolving structural, data, and control hazards)
  8. Caches (e.g., block size, associativity, and optimizing code for caches)
  9. Virtual memory and disks
  10. Survey of approaches to parallelization (e.g., SIMD, multi-core, cache coherence)

Required, Elective, or Selected Elective

Required

Last updated

4/1/2019by Geoffrey Lindsay Herman