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CS 433 - Computer System Organization

Spring 2020

Computer System OrganizationCS433S331405LCD31400 - 1515 T R  1109 Siebel Center for Comp Sci Christopher Wardlaw Fletcher
Computer System OrganizationCS433S431407LCD41400 - 1515 T R  1109 Siebel Center for Comp Sci Christopher Wardlaw Fletcher
Computer System OrganizationCSE422S331408LCD31400 - 1515 T R  1109 Siebel Center for Comp Sci Christopher Wardlaw Fletcher
Computer System OrganizationCSE422S431409LCD41400 - 1515 T R  1109 Siebel Center for Comp Sci Christopher Wardlaw Fletcher

Official Description

Computer hardware design and analysis and interface with software. Advanced processor design, including superscalar, out-of-order issue, branch prediction, and speculation. Memory hierarchy design, including advanced cache optimizations, main memory, and virtual memory. Principles of multiprocessor design, including shared-memory, cache coherence, synchronization, and consistency. Other advanced topics depending on time; e.g., GPUs and accelerators, warehouse computers and data centers, security. Course Information: Same as CSE 422. 3 undergraduate hours. 4 graduate hours. Prerequisite: CS 233.

Course Director


Computer Architecture: A Quantitative Approach, 6th Ed, by John L. Hennessy and David A. Patterson

Learning Goals

Understand design principles and methods used in contemporary processors and memory systems and apply them to new designs. (1), (2)
Evaluate the performance of a modern computer (1), (2)
Determine sources of potential performance bottlenecks in a processor design and determine techniques to address them. (1), (2)
Reason about sources of low memory system performance for a workload and determine techniques to address them (1), (2)
Evaluate tradeoffs between hardware and software techniques to achieve a performance goal (1), (2), (6)
Understand requirements for a correct parallel program and methods for supporting them in hardware. (1), (2), (6)

Topic List

Fundamental concepts related to performance, power, reliability, cost vs. price
Basic pipeline structure: some review from pre-requisite, multicyle functional units, static branch prediction, handling interrupts
Instruction-level parallelism: hardware techniques (e.g., dynamic scheduling, superscalar, dynamic branch prediction, handling precise interrupts)
Instruction-level parallelism: software-driven techniques (e.g., loop unrolling, trace scheduling, predication, memory access reordering)
Advanced concepts in cache design (e.g., prefetching, lockup-free caches, multilevel caches)
Main memory and virtual memory
Multiprocessors/multicore: parallelism models
Cache coherence: snoopy and directory solutions
Memory consistency models
Data parallel architectures

Assessment and Revisions

Revisions in last 6 years Approximately when revision was done Reason for revision Data or documentation available?
Removed details on instruction set architectures 2008 Much of this material was covered in 232 and instruction sets are no longer considered the key determinant of performance. The course still includes a summary of the main aspects of instruction sets. Discussion with 232 instructor and industry trends.
Removed basics of I/O, networks Around 2009 I/O basics were covered in 232 and networks overlapped significantly with operating systems. Removing this material enabled more detail of core architecture topics.
Introduced power and reliability as design constraints 2008 Reflects increased importance of power/reliability in industry practice The importance of power and reliability is well documented in research and industry literature.
Added multithreading/hyperthreading Introduced around 2010, but more details added around 2012 This technique was being increasingly implemented in commercial processors. Industry literature documents this trend.
Graduate students do a project requiring researching and presenting the design of a contemporary processor - undergraduate students are required to attend these presentations. These projects used to involve a single component of a processor. Now students are required to present the entire architecture (the core, memory hierarchy, and multicore aspects). This provides all students with a unified picture of how material learned in class is applied in practice. The processors covered change with new product releases. 2009 This was based on student feedback. They expressed they would like to see how a full system operates.
Removing the material described above enabled more details and class interaction on material covered, with changing emphasis depending on industry practice (e.g., more current emphasis on multicore). Ongoing.

Required, Elective, or Selected Elective

Selected Elective.

Last updated

2/10/2019by Sarita V. Adve