CS 398 - Data Driven Discovery

Spring 2019

Deep LearningCS398DL69481LEC30800 - 0920 T R  1404 Siebel Center for Comp Sci Justin A Sirignano
Machine LearningCS398EJP65174LCD31700 - 2000 F  ARR Danville IL Rebecca Ginsburg
Matt Zhang
Introduction to Data ScienceCS398IDU68294LCD31400 - 1550 M  126 Grad Sch of Lib & Info Science Victoria Stodden
Deep LearningIE398DL69146LEC30800 - 0920 T R  1404 Siebel Center for Comp Sci Justin A Sirignano
Introduction to Data ScienceIS457AG67407LCD41400 - 1550 M  126 Grad Sch of Lib & Info Science 
Introduction to Data ScienceIS457AU67659LCD41400 - 1550 M  126 Grad Sch of Lib & Info Science 
Introduction to Data ScienceSTAT430AG69375LCD41400 - 1550 M  126 Grad Sch of Lib & Info Science 
Introduction to Data ScienceSTAT430AU69376LCD31400 - 1550 M  126 Grad Sch of Lib & Info Science 

Official Description

Subject offerings of new and developing areas of knowledge in computer science intended to augment the existing curriculum. See Class Schedule or departmental course information for topics and prerequisites. Course Information: May be repeated in the same or separate terms if topics vary.

Course Director


Computer Organization and Design, Revised Fourth Edition, Fourth Edition: The Hardware/Software Interface by Patterson & Hennessy

Learning Goals

be able to design modest combinational circuits (20 - 30 gates) from an natural language (e.g., English) specification (b) (c)
be able to design finite state machines of moderate complexity (~10+ states) from a natural language specification. Furthermore, they should be able to implement these FSMs using a collection of gates and flip flops. (b) (c)
be able to analyze the design of a simple processor, specify the control signals for supported instructions, and modify it to implement new instructions. (b) (c)
be able to translate small (20 line) C programs that include recursion and pointers into MIPS assembly, observing calling conventions and stack management. (c) (k)
be able to write code that uses memory-mapped I/O and interrupts given interface documentation. (c) (k)
be able to demonstrate an understanding of the performance pitfalls of pipelined processors with cache memory systems by predicting the performance of code fragments on simple pipelines and cache memory systems. (b)
be able to optimize the cache performance of a simple loop nest through cache-aware programming techniques (b) (c)
be able to recognize synchronization, coherence, and consistency pitfalls that could impact the execution's result or performance of simple programs executing on a shared memory parallel processor. (b)
be able to work in small groups on open ended problems (b) (d)

Topic List

Combinational Logic Design
Sequential Logic Design
Computer Organization
Assembly Language
I/O and interrupts
Caching and Virtual Memory
Cache-Aware Programming
Hardware support for Parallel Programming (brief intro to coherence, consistency and atomic operations)

Assessment and Revisions

Revisions in last 6 years Approximately when revision was done Reason for revision Data or documentation available?

Required, Elective, or Selected Elective


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