Architecture, Compilers, and Parallel Computing

a supercomputer installationAs we approach the end of Moore’s Law, and as mobile devices and cloud computing become pervasive, all aspects of system design—circuits, processors, memory, compilers, programming environments—must become more energy efficient, resilient, and programmable.

Our research groups explore energy efficiency via low-voltage design techniques, specialized hardware accelerators, adaptive runtime techniques in high performance computing, efficient memory architectures for heterogeneous mobile systems, novel architectures for exascale systems, and other projects. We examine resilience through tolerating variation during chip fabrication, failure-tolerant processor architectures, scalable resilience protocols, and automated software debugging and recovery techniques. We explore programmability through architectural support for synchronization, automatic parallelization and vectorization, performance-portability for heterogeneous mobile systems, high-performance implementations of scripting languages, and highly scalable parallel run-time systems.

In addition to collaborating with major companies, our software artifacts like LLVM and Charm++ are widely used in industry, government labs, and academic research.

CS Faculty and Their Research Interests

Sarita Adve parallel computing, memory architecture, power- and reliability-aware architectures 
Vikram Adve compiler infrastructures and techniques, secure architectures, heterogeneous systems 
Christopher Fletcher (joining fall 2017) secure architecture
Maria J. Garzaran compilers, hardware-software interaction, software frameworks for high-performance computing 
William Gropp programming models and systems for parallel computing 
Laxmikant Kale large-scale parallel systems; runtime systems, tools, and frameworks for high-performance computing 
David Padua compiler techniques for parallel computing 
Rob A. Rutenbar accelerator architecture, approximate computing, FPGA, VLSI, CAD 
Marc Snir large-scale parallel systems, algorithms, and libraries 
Edgar Solomonik communication complexity
Josep Torrellas parallel architectures, power- and reliability-aware hardware/software architectures 
Craig Zilles compilers, dynamic optimization, computer science education 

Affiliate Faculty

Deming Chen, Electrical & Computer Engineering hardware/software co-design for system-on-chip; reconfigurable computing; GPU computing and optimization
Wen-mei Hwu, Electrical & Computer Engineering HPC and parallel systems, compilers, GPU programming
Nam Sung Kim, Electrical & Computer Engineering non-conventional computer architecture: bio-inspired, molecular, cellular, and analog-digital hybrid computing 
Rakesh Kumar, Electrical & Computer Engineering power- and reliability-aware architectures, approximate computing 
Steve Lumetta, Electrical & Computer Engineering parallel computing, architecture, reliability, architectures for genomic applications 
Sanjay Patel, Electrical & Computer Engineering high-performance and parallel systems
Shobha Vasudevan, Electrical & Computer Engineering system verification and security; analog and digital hardware validation 
Martin Wong, Electrical & Computer Engineering computer-aided design of integrated circuits

Architecture, Compilers, and Parallel Computing Research Efforts and Groups

Architecture, Compilers, and Parallel Computing News

Josep Torrellas

Torrellas Elected AAAS Fellow

November 21, 2016   Josep Torrellas is one of six University of Illinois at Urbana-Champaign faculty members who have been elected 2016 fellows of the American Association for the Advancement of Science.
Computer Science Investitures

CS set to honor four distinguished faculty with named chairs and professorships

November 14, 2016   One of the highest honors the campus can bestow, named chairs and professorships acknowledge outstanding faculty research, service, and education accomplishments.

Beyond Silicon: Squeezing More Out of Chips

October 30, 2016  

The New York Times - Researchers are turning to more efficient algorithms as chipmakers approach the physical limits of silicon. CS Professor Marc Snir and collaborators at Argonne National Lab look to trade precision for efficiency to realize energy savings in supercomputing, while Ali Farhadi (PhD CS ’11) leads work on efficient neural networks.

CS graduate student Matthew Sinclair with 1986 Turing Award winner Robert Tarjan.

Meeting the rock stars of CS and mathematics fields

October 24, 2016   Three CS @ ILLINOIS graduate students were among 200 young researchers worldwide to participate in the annual Heidelberg Forum.
CS Professor Bill Gropp

Gropp Recognized for Major Contributions to High Performance Computing

October 6, 2016   CS Professor Bill Gropp has been named the recipient of the 2016 ACM/IEEE Computer Society Ken Kennedy Award.