8/9/2010
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University of Illinois computer science professor Craig Zilles and computer science PhD student Naveen Neelakantam took home Best Paper honors at the recent Architectural Support for Programming Languages and Operating Systems. Their paper, entitled “A Real System Evaluation of Hardware Atomicity for Software Speculation” was one of 3 Best Papers named at the conference.
With Moore’s Law stretched to capacity, hardware designers face the daunting task of finding new ways to increase processor performance without undue increase in complexity and power usage.
“New compiler optimizations offer an opportunity to both improve the performance of a single thread as well as reduce power consumption,” said Zilles. “But developing optimizations that surpass the state of-the-art typically involves complex implementations that are difficult to develop and that complexity can be a source of bugs.”
Therefore, cost-effective hardware that can aid a compiler in achieving new heights of performance is of particular interest. One such hardware mechanism is hardware atomicity. Hardware atomicity enables a processor to take a checkpoint of its current state and continue executing for a few hundred instructions and then deciding to either make the results of the execution since the checkpoint visible at once or discard them and return to the checkpoint state. This powerful capability is actually a modest extension of the existing support for speculative execution found in most processors.
Using hardware atomicity, a compiler can construct “atomic regions”, which in turn help a compiler optimize program paths by removing paths that are rarely used. This helps to increase performance for most operations, without requiring additional power consumption. In the event that the less-used path is needed in the future, the hardware simply rolls back the atomic region and resumes executing the code as normal.
In the paper, the team evaluated the atomic region compiler abstraction by incorporating it into a commercial system, the Transmeta Efficeon processor. They found that atomic regions are simple and intuitive to integrate an x86-to-VLIW binary-translation system. Furthermore, they found that doing so trivially enables additional optimization opportunities beyond that achievable by a high-performance dynamic optimizer.
They evaluated using full reference runs of the SPEC CPU2000 integer benchmarks and found that atomic regions enable up to a 9% (3% on average) improvement beyond the performance of a tuned product.
These performance improvements were achieved without any negative side effects. Performance side effects such as code bloat are absent with atomic regions; in fact, static code size is reduced. The hardware necessary is synergistic with other needs and was already available on the commercial product used in our evaluation. Finally, the software complexity is minimal as a single developer was able to incorporate atomic regions into a sophisticated 300,000 line code base in three months, despite never having seen the translator source code beforehand.
The team found that atomic regions can suffer from severe performance penalties if misspeculations are left uncontrolled, but that a simple software control mechanism is sufficient to reign in all detrimental side-effects. To reduce the cost of misspeculation, Zilles and Neelakantam plan implement a misspeculation recovery mechanism that redirects execution to a non-speculative translation.
The complete paper can be viewed at: http://portal.acm.org/citation.cfm?id=1736026&coll=GUIDE&dl=GUIDE&CFID=98041413&CFTOKEN=43565908&ret=1#Fulltext